Regviz

NXP Semiconductors /LPC800 /GPIO_PORT /CLR0

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLR0

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/LPC800/GPIO_PORT/CLR0#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLRP00RESERVED

Description

Clear port 0

Fields

CLRP0

Clear output bits: 0 = No operation. 1 = Clear output bit.
RESERVED

Reserved.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data